[Libre-soc-dev] Libre-SOC SVP64 first Cray-style Vector loop successful

[Veera]

On Sun, Mar 07, 2021 at 01:24:51PM +0000, Luke Kenneth Casson Leighton wrote:
> with many thanks and congratulations to Cesar for getting the first basic
> Cray-style Vector Loop operational in HDL, on top of OpenPOWER v3.0B and
> passing its first unit tests.
> 

Congratulations to Cesar and team!

> the Simulator ISACaller was functional three weeks ago and has been used to
> verify the HDL's functionality through co-simulation:
> 
> an identical co-simulation process is planned to be applied for qemu,
> power-gem5 and Microwatt when adding SVP64.  qemu co-simulation of
> OpenPOWER v3.0B is *already* performed (and has found obscure bugs in qemu!)
> 
> our next steps are to add:
> 
> * LD/ST and other pipeline unit tests
> * Single and Twin Predication
> * Polymorphic Element Width overrides (uint8/16/32, FP16, BF16)
> * Saturation, Mapreduce, and other advanced modes
> 
> medium term:
> 
> * Scalar v3.0B Bitmanipulation extensions suitable for cryptographic, Audio
> and Video and other uses (Vectorisation of these now comes "for free"!)
> * Scalar v3.0B IEEE754 FP Transcendentals (SIN, COS, ATAN2, LOG1P) which
> again become inherently and automatically Vectorised
> * 3D Texturisation opcodes suitable for Vulkan Khronos Group Compliance
> 
> longer term:
> 
> * SV-REMAP provides 2D and 3D Matrix register remapping
> * Instruction Prefix remapping similar to hardware compression
> 
> all of this is achieved without modifying the Scalar OpenPOWER v3.0B ISA in
> any way, without requiring (eliminating and superceding) any of the SIMD
> (VSX) ISA, merely adding a new "Vector Context" inside v3.1 style EXT01 64
> bit prefixes.
> 
> we are tracking the implementation progress here, including gcc, power-gem5
> and would love to see Microwatt as well, as time permits:
> 
> https://libre-soc.org/openpower/sv/implementation
> 
> l.
> 

Regards,
Veera