[Libre-soc-dev] daily kan-ban update 01mar2021

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Mon, Mar 1, 2021 at 7:22 PM Tobias Platen
<libre-soc at platen-software.de> wrote:
>
> On Mon, 1 Mar 2021 19:08:30 +0000
> Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
>
> > On Mon, Mar 1, 2021 at 6:05 PM Tobias Platen
> > <libre-soc at platen-software.de> wrote:
> > >
> > > today: more work on MMU integration
> >
> > great.  my feeling is that it's going to be easier to have something
> > side-by-side to compare against (ISACaller)  you _could_ stare
> > manually for hours at debug logs.  an alternative is to get ISACaller
> > RADIX support added, then let simulations do all the work.
> >
> > l.
> After adding the RADIX support, I can do faster debugging.
> Today I found out that the "fix" for #607 causes my unit test to break.

2730d379d0 - rom mmu test works (doesn't end, but works)


> I also know that there are more bugs in my code, that need to be debugged first.

understood.

ok what's going on.

lkcl at fizzy:~/src/libresoc/soc/src/soc$ grep -r mmu0_spr_dec
simple/core.py:            self.decoders["mmu0"].mmu0_spr_dec =
self.decoders["spr0"]

ah.  right.  this is a bad hack :)  it needs special commenting and an
explanation.   i've reverted this below for now:


-        if self.fn_name=="MMU":
-            # mmu is special case: needs SPR opcode as well
-            mmu0 = self.mmu0_spr_dec
-            with m.If(((mmu0.dec.op.internal_op == MicrOp.OP_MTSPR) |
-                       (mmu0.dec.op.internal_op == MicrOp.OP_MFSPR))):
-                comb += self.do_copy("insn_type", mmu0.op_get("internal_op"))
-            with m.Else():
-                comb += self.do_copy("insn_type", self.op_get("internal_op"))
-        else:
-            comb += self.do_copy("insn_type", self.op_get("internal_op"))
+        # FIX https://bugs.libre-soc.org/show_bug.cgi?id=607
+        comb += self.do_copy("insn_type", self.op_get("internal_op"))