[Libre-soc-dev] Luke: jtag testing

[Luke Kenneth Casson Leighton]

On Mon, Mar 1, 2021 at 5:53 PM Cole Poirier <colepoirier at gmail.com> wrote:

> A reminder that I need your input on the jtag setup
> (https://bugs.libre-soc.org/show_bug.cgi?id=517) and jtag testing
> (https://bugs.libre-soc.org/show_bug.cgi?id=605) bug reports and
> cannot proceed any further until you comment.

got it.  the FPGA and ASIC variant is near-identical, it should be
clear to substitute "FPGA" for "sim.py".  also there are soc.debug
utils such as this
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/firmware_upload.py;hb=HEAD

l.