[Libre-soc-dev] Question about some "empty" components in the design

[Jean-Paul Chaput]

I did use Yosys 0.9 git 049e3ab.

It annonce itself as Yosys 0.9+4008 (in it's banner).


On Mon, 2021-06-28 at 11:00 +0100, Luke Kenneth Casson Leighton wrote:
> On 6/28/21, Marie-Minerve Louerat <Marie-Minerve.Louerat at lip6.fr> wrote:
> > Hello,
> > 
> > While doing the Layout Versus Schematic check of the whole design,
> > 
> > I found these  components which do not instantiate anything:
> > 
> >   cmpt_dummy.vst
> > 
> 
> dummy should be blank, it is "do nothing"
> 
> > cmpt_rdpick_curu_cr_b.vst
> >   cmpt_rdpick_curu_cr_c.vst
> >   cmpt_rdpick_curu_full_cr.vst
> >   cmpt_rdpick_supuru_spr1.vst
> >   cmpt_rdpick_xueuru_xer_ov.vst
> >   cmpt_wrpick_curu_full_cr.vst
> >   cmpt_wrpick_supuru_spr1.vst
> >   cmpt_wrpick_sutuautueu_msr.vst
> >   cmpt_wrpick_sutuautueu_svstate.vst
> 
> all of these are "priority pickers" for register file read/write enable.
> 
> if there are two inputs then something is definitely wrong.
> 
> > 
> > They have just the interface with terminals.
> > 
> > Is that a problem or not?
> 
> i will look at the verilog.
> 
> if they are picking only one thing, then, well, that is just "a wire"
> and chances are high they have been optimised out.
> 
> if they have several inputs then it sounds like something gone wrong with yosys.
> 
> will take a look.  thank you for finding this Marie-Minerve
> 
> l.
> 
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