[Libre-soc-dev] Question about some "empty" components in the design
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Jun 28 11:00:07 BST 2021
On 6/28/21, Marie-Minerve Louerat <Marie-Minerve.Louerat at lip6.fr> wrote:
> While doing the Layout Versus Schematic check of the whole design,
> I found these components which do not instantiate anything:
dummy should be blank, it is "do nothing"
all of these are "priority pickers" for register file read/write enable.
if there are two inputs then something is definitely wrong.
> They have just the interface with terminals.
> Is that a problem or not?
i will look at the verilog.
if they are picking only one thing, then, well, that is just "a wire"
and chances are high they have been optimised out.
if they have several inputs then it sounds like something gone wrong with yosys.
will take a look. thank you for finding this Marie-Minerve
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