[Libre-soc-dev] SVP64 Scalar Map-reduce mode added
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Jun 9 18:36:57 BST 2021
Lauri i've added an example scalar map-reduce, it's dead easy:
sv.fmuls/mr 1, 2.v, 1
it was actually amazingly easy to add: simply go:
"if mapreduce mode then allow vector adds even when the output is a scalar"
if you can avoid using the *vector* map-reduce mode for now that would
be good. Vector map-reduce mode is:
sv.fmuls/mr 1.v, 10.v, 1.v
and it will use the registers 1, 2, 3, .... as *intermediate* locations in
to (optimally) perform a parallel tree-reduction. and also allow
the middle of it.
also don't use the sub-vector variant, yet:
sv.fmuls/mr/vec4 1, 2.v, 1
because i haven't done that mode, either.
if you need any of those let me know?
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