[Libre-soc-dev] SVP64 Scalar Map-reduce mode added

[Luke Kenneth Casson Leighton]

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=a73dcd90746856a39a53ced9b4335409d3be27b6

Lauri i've added an example scalar map-reduce, it's dead easy:

     sv.fmuls/mr 1, 2.v, 1

it was actually amazingly easy to add: simply go:
"if mapreduce mode then allow vector adds even when the output is a scalar"

if you can avoid using the *vector* map-reduce mode for now that would
be good.  Vector map-reduce mode is:

     sv.fmuls/mr 1.v, 10.v, 1.v

and it will use the registers 1, 2, 3, .... as *intermediate* locations in
order
to (optimally) perform a parallel tree-reduction.  and also allow
interrupts in
the middle of it.

also don't use the sub-vector variant, yet:

    sv.fmuls/mr/vec4 1, 2.v, 1

because i haven't done that mode, either.

if you need any of those let me know?

l.