[Libre-soc-dev] Unexpected clock connexions.
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Jun 4 13:05:15 BST 2021
> If the clock is badly connected, I should be able
> to see it in the P&R layout
thanks to Staf for making me think, we worked out that making no
attempt to use nmigen Clock Domains "fixed" rhe problem.
also, Staf noticed that the peripherals have to be run at the PLL speed.
this was where the majority of DFFs at the wrong speed would have come from.
only the RESET line should now cross domains, and it should go through
JTAG and DMI *ONLY*.
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