[Libre-soc-dev] Unexpected clock connexions.

Jean-Paul Chaput Jean-Paul.Chaput at lip6.fr
Fri Jun 4 11:06:19 BST 2021

On Fri, 2021-06-04 at 11:44 +0200, Staf Verhaegen (FibraServi) wrote:
> On 3/06/2021 23:04, Luke Kenneth Casson Leighton wrote:
> > Staf, attached patch for your review, it is a simple rename:
> > 
> > * sys_clk to sys_clk_0
> > * ref_clk returns back to sys_clk
> Reason I did not do this is that have to be sure to rename all 
> occurrences of sys_clk internal signal otherwise you would end up with 
> part still connected directly to sys_clk. With my change it was not 
> needed to track down all exisinting of sys_clk so I didn't. I agree that 
> number of occurences is low so your patch looks fine.

  If the clock is badly connected, I should be able to see it in the
  P&R layout. All DFFs must be connected to the leafs of the H-Tree
  and the only remaining connexions are between I/O pad, PLL and the
  root of the H-Tree. Can track them manually.

> I did some verification:
> * soc-cocotb-sim commit 2957b26
> * I just added Verilog model for pll in bypass
> * The IDCODE and scan chain test run on changed netlist
> * These tests don't actually test anything driven by sys_clk.
>    Luke, were you able to do DMI test with cocotb or verilator directly ?


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