[Libre-soc-dev] Unexpected clock connexions.
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Jun 3 21:42:10 BST 2021
took a look, it's very straightforward, and clear.
unfortunately the chsnge of the ls180 signal named "sys_clk" has
knock-on implications, aboit 8 different code locations are needed in
several separate repositories, in the coriolis2 settings, pinouts, and
it would be much less work for both myself and Jean-Paul if the rename
was done such that sys_clk remains the same in ls180.
is that practical / possible? if not we can probably luve with it.
On 6/3/21, Staf Verhaegen (FibraServi) <staf at fibraservi.eu> wrote:
> On 3/06/2021 17:27, Luke Kenneth Casson Leighton wrote:
>> * soclayout commit cfec1eccb660838
>> * nmigen simulation confirmed functional
>> * verilator test simulation with "fake" PLL confirmed functional
>> * nsxlib build underway is currently doing "Global Placement"
> * soclayout commit 227a0f69bd5065d
> * This is a proposal for a minimal patch to reroute the clock.
> * Two extra files with _recon.v ending; small verifiable diff
> * Could perform synth in yosys with new files; further verification is
> for tomorrow
> Chips want to be free.
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