[Libre-soc-dev] Unexpected clock connexions.
Staf Verhaegen (FibraServi)
staf at fibraservi.eu
Thu Jun 3 21:07:26 BST 2021
On 3/06/2021 17:27, Luke Kenneth Casson Leighton wrote:
> * soclayout commit cfec1eccb660838
> * nmigen simulation confirmed functional
> * verilator test simulation with "fake" PLL confirmed functional
> * nsxlib build underway is currently doing "Global Placement"
* soclayout commit 227a0f69bd5065d
* This is a proposal for a minimal patch to reroute the clock.
* Two extra files with _recon.v ending; small verifiable diff
* Could perform synth in yosys with new files; further verification is
Chips want to be free.
More information about the Libre-soc-dev