[Libre-soc-dev] Unexpected clock connexions.

Jean-Paul Chaput Jean-Paul.Chaput at lip6.fr
Thu Jun 3 15:54:44 BST 2021

Didn't stumble on that one, but will do.

On Thu, 2021-06-03 at 15:40 +0100, Luke Kenneth Casson Leighton wrote:
> Jean-Paul apologies can you also add name conversion for "ref" to "ref_v"
> just like "out" / "out_v" it turns out "ref" is a Verilog keyword.
> l.
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