[Libre-soc-dev] Unexpected clock connexions.

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Jun 3 15:40:58 BST 2021


Jean-Paul apologies can you also add name conversion for "ref" to "ref_v"
just like "out" / "out_v" it turns out "ref" is a Verilog keyword.

l.


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