[Libre-soc-dev] data/instruction cache consistency

[Jacob Lifshay]

I found this very interesting document describing instruction fetch, JITs
and some of the issues that CPUs can run into:
https://github.com/riscv/riscv-j-extension/blob/master/id-consistency-proposal.pdf

I think it's worth reading even though it's about RISC-V instead of
OpenPower.

Interestingly enough, Paul Mackerras helped out with it some...

Jacob