[Libre-soc-dev] synchronised incremental SV development planning

[Luke Kenneth Casson Leighton]

Rc=1 now works, in ISACaller.  there's still a bit to do:

* disable OE=1 for CRs when SVP64 is enabled, to stop RMW hazards on XER.so
* pick a suitable multiple of 16 location for starting Rc=1 Vectors of CRs.

l.