[Libre-soc-dev] synchronised incremental SV development planning

[Luke Kenneth Casson Leighton]

cesar and i are slowly incrementally putting SVP64 loops into TestIssuer.
 we have it now as 3 FSMs: fetch, issue, execute.  the issue FSM is where
VL loops occur.  later these three FSMs can be pipelined very easily.

yesterday i did the autogeneration of a microwatt sv_decode.vhdl which
matches the decode1.vhdl exactly, adding sv_in1/2/3/out where decode1.vhdl
has in1/2/3/out.

ISACaller has had VL loops for over a week now.  the next thing to consider
adding is predication, it looks like ISACaller will "run ahead" of all
other development, which is a good thing.  Twin Predication will ve fun.

an SVP64 RM Field decoder is needed, to recognise the predicate, as well as
whether zeroing should be done.  this will be interesting to implement.

power-gem5 will be about a month before it becomes mainstream.  we may have
to start before that occurs, and rebase.

what is everyone else doing, we have a lot to get done.  extra unit tests,
much more.

l.


-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68