[Libre-soc-dev] Quick help

[Luke Kenneth Casson Leighton]

On 9/25/20, Cole Poirier <colepoirier at gmail.com> wrote:
> On Fri, Sep 25, 2020 at 1:34 PM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
>> that looks right to me.
>
> Thanks Luke, SUPER helpful, now I know the bug lies elsewhere...
> ICache now 'works' aka runs passes 'assert valid' fails the second
> assert, exciting progress for me.

niiice.

> Time for some gtkwave debugging :)

yeh this was paainful took me 3 days gtkwave traces.

i strongly recommed lookigng up "jeanthom nmigen Display" and patching
nmigen with that, link is in nmutil

then add sync += Display something look how it is done in dcache.py

this is.absolutely invaluable to finding out what the hell is going on.

oh btw notice that i chopped 3 bits off the wishbone adr in dcache.py

the microwatt use of wishbone is NOT compliant with WB4 spec.

they put the LSBs onto the adr bus that are covered by the sel bits.

l .