[Libre-soc-dev] Attempting to run sim error

[Cole Poirier]

Hi Luke,

Not sure if this is useful, but it might be. I'm trying to run the
command to generate the libresoc.v file necessary for sim.py with the
following command and getting the following error traceback. I'm not
sure if this is just a missing argument in the init constructor in the
c4mjtag tap, or if your maintaining a local fork of that? Anyway, if
it's not an issue and you're still working on the time-sensitive
issues for the dec-2-fallback code freeze, don't worry about filling
me in until later :)

`soc$ python3 src/soc/simple/issuer_verilog.py
src/soc/litex/florent/libresoc/libresoc.v`
```
Traceback (most recent call last):
  File "src/soc/simple/issuer_verilog.py", line 35, in <module>
    dut = TestIssuer(pspec)
  File "/home/colepoirier/src/soc/src/soc/simple/issuer.py", line 84,
in __init__
    self.jtag = JTAG()
  File "/home/colepoirier/src/soc/src/soc/debug/jtag.py", line 44, in __init__
    name="jtag_wb")
  File "/home/colepoirier/opt/c4m-jtag/c4m/nmigen/jtag/tap.py", line
621, in add_wishbone
    name=name, src_loc_at=src_loc_at+1)
TypeError: __init__() got an unexpected keyword argument 'src_loc_at'
```

Cole