[Libre-soc-dev] change of tapeout date, and roadmap for 180nm ADIC

[Staf Verhaegen]

Luke Kenneth Casson Leighton schreef op wo 23-09-2020 om 19:03 [+0100]:

> staf says that with no clock timing constraint checking in coriolis2
> it is unwise to try multiple clocks.  therefore no PLL and only
> digital dividing of an incoming signal, 50mhz is perfectly reasonable.

The PLL will be included but what we agreed upon is that only one
power/clock domain is allowed on the prototype so no cross-domain
problems can occur in the design. The JTAG wishbone interface has been
specifically designed to be able to avoid possible problem if the speed
if not too high compared to main CPU clock.

greets,
Staf.