[Libre-soc-dev] big.little GPU PowerISA architectures

[Luke Kenneth Casson Leighton]

hi this publicly-raised question is primarily for the Board of the
OpenPOWER Foundation.

https://www.phoronix.com/forums/forum/phoronix/latest-phoronix-articles/1207878-libre-soc-still-persevering-to-be-a-hybrid-cpu-gpu-that-s-100-open-source?p=1208017#post1208017

a fascinating idea came up on phoronix which suits a GPU architecture
extremely well: subsets of PowerISA on "little" cores, with extremely
wide Vector Processing, and tiny Instruction Caches, but otherwise
full SMP.  even some "scalar" (standard UNIX SMP) workloads would
still then run on those cores, and if an instruction is encountered
which they cannot cope with, the "illegal instruction" raised would
have them context-switched to a "big" core where they would then
successfully complete.

the problem is that such a commercially competitive architecture runs
smack into the restrictive set of "Compliancy" definitions, which only
takes into consideration four possible (pre-existing) use-cases for
PowerISA (AIX, UNIX, Embedded, Embedded-fixedpoint)

where can this be discussed in a way that respects our commercial
business objectives for "Full Transparency", such that it may be taken
into consideration and if needs be the v3.1B Specification updated to
take our business objectives into account, and thus expand the reach
of the OpenPOWER ISA into markets that it presently cannot achieve?

many thanks for your kind consideration,

l.

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