[Libre-soc-dev] [Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[Cole Poirier]

On Wed, Sep 16, 2020 at 3:14 PM bugzilla-daemon--- via libre-soc-bugs
<libre-soc-bugs at lists.libre-riscv.org> wrote:
>
> https://bugs.libre-soc.org/show_bug.cgi?id=490
>
> Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:
>
>            What    |Removed                     |Added
> ----------------------------------------------------------------------------
>            Priority|Highest                     |High
>            Severity|blocker                     |normal
>
> --- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
> ok i cranked the priority down just a leeetle bit :)
>
> i also just committed some preliminary changes, cut out the pins not needed,
> put in that verilog stuff we talked about
>
> commit 093ddebb6ba44f3edd291d699d775c6821b8d620 (HEAD -> master, origin/master)
> Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> Date:   Wed Sep 16 22:54:15 2020 +0100
>
>     make a start on LS180 platform

Great! Just committed my translation pass of the JTAGToDMI from
microwatt, didn't bother with formatting, and left a few things I
didn't understand untranslated, should all be obvious in the commit.
As far as I understand that completes what we talked about on our call
today, but I do think my understanding is mistaken so please let me
know what is left for me to do :)

Cole