[Libre-soc-dev] Silly question

[Luke Kenneth Casson Leighton]

On Mon, Sep 14, 2020 at 6:40 PM Cole Poirier <colepoirier at gmail.com> wrote:
>
> On Mon, Sep 14, 2020 at 10:34 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> > a nmigen Signal is the representation used for vhdl std_logic and integer
> > iirc, so to_integet most likely translates to a no-op.
>
> Ok with you there, I guess what I really need to know is the nmigen
> way of interpreting an nmigen Slice as a python integer value so that
> it can be used as a slice index. Currently getting the following error
> with the following code (icache lines 366-371):

the very first thing you should do, Cole, on any collaborative
project, when waking up, is "git pull".

if you had done "git pull" this morning you would have found that i
had looked at the commit log and fixed the issue that you're still
trying to resolve (and one other).

i would have sent a message however i have very bad RSI at the moment
and it is very painful to type.

l.