[Libre-soc-dev] daily kan-ban update 10sep2020

[Cole Poirier]

On Thu, Sep 10, 2020 at 3:03 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> yesterday call with microwatt team, discussed VSX and noted in particular
> that glibc6 ppc64le has assumed the ABI requires VSX (SIMD). this is a
> major problem for us as it adds around 700 instructions, none of which are
> going to be used.

Yes, as I believe you said in your mail about this to
OpenPOWER-HDL-Cores, this would be an 8-10 month setback for not just
no benefit but a substantial increase in the complexity of the decoder
such that it might have to be made into a two stage pipeline. Not to
mention the (I assume? please explain if I'm way off) massive area
(but not power I assume as we won't ever use them because of SV)
increase from implementing those 700 instructions. It definitely seems
like vector instructions should be optional for compliance with all
but the massive power-hungry HPC server processors like POWER9/10.
I'll anxiously await a reply from (likely) one of the microwatt team
members, and ultimately the architectural working group late this
year/early next year. I am, as you say Luke, feeling a bit twitchy
about this.

> today finished and uploaded the video for OpenPOWER NA 2020 which is on
> 15th sep.

Fantastic! I just checked your youtube channel and it's not there...
Is it on the wiki somewhere? Or somewhere else? Would you mind linking
it/sending it to me, I'd like to peruse it in my down-time this
evening... or likely next as it's 1 am where you are ;)

> also did more on dcache.py

Thank you, reviewing it now.

> if we are to meet the oct 2020 deadline we need to seriously focus and get
> the peripheral set done.  litex looks to be the best way to do that however
> it means wrapping random bits of verilog in litex / migen.

Right. Bug 412 - "set up litex for peripherals and linking to core"
has been closed as PAYMENT_PENDING because I assume that was just for
getting the initial litex working (i.e. your 3 weeks of very
meticulous bug hunting). Should I create a new bug for the remaining
peripherals (are they litex or are they external verilog code to be
wrapped with litex?), that can serve as the top-level/coordination bug
for this? If so please provide a name as I don't understand the
problem well enough to name the bug. Then, I can create the bug and
you can fill in the details in the description?

Cole