[Libre-soc-dev] daily kan-ban update 08sep2020

[Luke Kenneth Casson Leighton]

tasks:

* https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1

yesterday:

* went over dcache.py (first pass)
* started on subsetting of PowerDecoder2 (columns and rows)

today:

* got PowerDecoder2 subsetting working (executes binaries in litex sim.py)

this is... complicated.  basically the PowerDecoder2 takes a 32 bit
instruction and expands it out into a massive bunch of wires.  64 bit
for the immediate RB for example.  N more bits here, N more bits
there.  this is far too much to route.

so instead, what i've done is: using the column-subsetting (which
limits which CSV columns get generated in the decoder) and
row-subsetting (which limits which Switch/Case statements get
generated), made it possible to generate PER-PIPELINE instruction
decoders.

therefore: rather than route 192+ wires across entire swathes of the
chip (to 12 separate pipelines), all you do is *PARTIALLY* decode the
instruction (enough to know which pipeline to deliver to), then route
the *raw* instruction (only 32-bit) over to the pipeline, and have it
*locally* decode *ONLY* the instruction fields that it actually needs.

this does mean however that immediates get decoded more than once, for
example.  given that it's local, i'm not concerned about that.  it's
the number of wires crossing the chip that's got to come down.

l.

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68