[Libre-soc-dev] Running the libre-soc CPU under cxxsim

[Cesar Strauss]

Greetings,

There is a new proposed fix in nMigen for a bug in cxxsim.

See:
https://github.com/nmigen/nmigen/issues/439#issuecomment-687930950

The test cases in that bug report now all pass.

Whitequark would like us to try the fix on our overall design, not just
the test cases on that bug report.

So, I think it would mean running the libre-SOC CPU under cxxsim.

Can we do it? Which unit test gives the most coverage? Would it be
src/soc/simple/test/test_issuer.py ?

To run cxxsim on a test case:

1) Compile yosys from master branch

2) On nmigen source dir:
    git branch -D cxxsim
    git checkout cxxsim

3) Apply the one-line patch at:
https://github.com/nmigen/nmigen/issues/439#issuecomment-687930950

4) On the test case, replace

    sim = Simulator(m)

with

    sim = Simulator(m, engine="cxxsim")

Optionally (just to avoid printing a warning), change

    from nmigen.back.pysim import Simulator, Delay, Settle

with

    from nmigen.sim import Simulator, Delay, Settle

Regards,

Cesar