[Libre-soc-dev] versa_ecp5.py P&R failure was daily kan-ban update 14oct2020

[Luke Kenneth Casson Leighton]

On 10/14/20, Cole Poirier <colepoirier at gmail.com> wrote:

> hopefully you get the gist of what I’m saying.

i do.  the reason i am doing the bisect is to find at what point the
FPGA upload stopped working.

because we use git anyone including you can go back through the
history.  plus, *before* you committed anything, i believe i said
latest master is not working.

> ok the missing pieces are that litex doesn't understand XICS
> interrupts, and they were in an unconfigured peripheral address
> location anyway.
> ```

do try not to lose indentation, btw.  it looks like you wrote that
because of no ">"s.

> i.e. if we need litex to be able to understand XISC,

not litex's problem / issue.  or it is, sort-of.

interrupts are handled by a generic "signal" that gets allocated to
litex peripherals on a per-bit basis.

however just raising an interrupt means that, well, duh, the core will
be interrupted.

and if the software has not been written *to* deal with that
interrupt, then guess what happens?

so this is why it is and is not litex's problem

> and if not what our ‘workaround’/alternative is.

try to run the microwatt xics.bin test in the fpga.

l.