[Libre-soc-dev] daily kan-ban update 10oct2020

[Luke Kenneth Casson Leighton]

On Sat, Oct 10, 2020 at 9:54 PM Cole Poirier <colepoirier at gmail.com> wrote:
>
> On Sat, Oct 10, 2020 at 1:32 PM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> >
> > On Sat, Oct 10, 2020 at 9:22 PM Cole Poirier <colepoirier at gmail.com> wrote:
> > >
> > > I'm trying to execute ./soc/litex/florent/versa_ecp5.py --build and
> > > getting a cryptic error about a missing port. Any idea what this might
> > > be?
> >
> > have a look in issuer_verilog.py and also in issuer.py
> >
> > > ```
> > > 4.4.3. Analyzing design hierarchy..
> > > Top module:  \versa_ecp5
> > > Used module:     \test_issuer
> > > ERROR: Module `test_issuer' referenced in module `versa_ecp5' in cell
> > > `test_issuer' does not have a port named 'gpio_wb__err'.
> >
> > no gpio wishbone port.
>
> Ah right... thank you.
>
> > you see in issuer_verilog.py, the option to enable "test_gpio"?  then
>
> No such variable test_gpio, do you mean:
> 32                          gpio=False, # for test purposes
>                               ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

yyep.

> No such variable gpio_en in issuer.py, do you mean:
>
> ```
> 138         # GPIO test peripheral
> 139         if self.gpio:
> 140             m.submodules.simple_gpio = simple_gpio = self.simple_gpio

yyep.

all these options really need to be enabled / disabled using getopt, really.

the other alterantive - in libresoc/core.py - is to comment this out:

        if variant != "ls180":
            self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)

but you also need to look for the location where that's used.

l.