[Libre-soc-dev] make run_sim failure

[Cole Poirier]

On Thursday, October 8, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On 10/8/20, Cole Poirier <colepoirier at gmail.com> wrote:
> > Hi Luke,
> >
> > I've been trying to successfully compile and run the litex-libre-soc
> > simulation for over a week
>
> question: why did you waste 6 days not communicating


Because I thought I was doing something wrong on my end and didn’t want to
interfere with your flow while you were working with JP and Staf very
intensely, but since yesterday you asked me to start doing jtag testing on
FPGA and my 85k LUT FPGA came today I thought I should make sure it worked.
I realize now how counterproductive this was, I’m sorry.


> that's a staggering 30% of the remaining time until the chip gets done.
>
> if you had asked 6 days ago you would have found out 6 days ago that i
> haven't had time to keep ls180soc.py and versa_ecp5.py and sim.py all
> in sync and all working because i am not getting enough help from
> everyone else to do so, given that i am only about 40% effective
> because of this virus.
>
> and i could have advised you, 6 days ago, of an approach on how to fix it.
>
> i will take a look (tomorrow, which is yet another day, 8% of
> available time until the deadline) and see what needs doing.
>

Understood. I’ll take a look in those files today and see if I can get it
working.

Cole