[Libre-soc-dev] efficient decoding algorithm for variable-length instructions

[Jacob Lifshay]

On Wed, Nov 25, 2020, 04:53 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Wed, Nov 25, 2020 at 6:06 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > I wrote out the following decoding algorithm for variable-length
> instructions:
> > https://libre-soc.org/openpower/sv/16_bit_compressed/decoding/
> >
> > It uses the 16/32/48/64-bit encoding that I proposed in earlier
> > emails. It has a circuit depth of O(log N) for a decoder that can
> > decode N instructions per cycle.
>
> excellent.
>
> just to check: https://libre-soc.org/openpower/sv/16_bit_compressed/
>
>     "Demo of encoding that's backward-compatible with PowerISA v3.1 in
> both LE and BE mode"
>
> i believe we determined yesterday that this is not true?  that 16/48
> (as i intuited/suspected" prevents and prohibits inter-mingling of
> v3.0B, v3.1B and 16/48-bit prefixed instructions without additional
> state (such as a VLE-like 64k page marker bit)?
>

You misunderstood me, the additional state is tracked as-if it is an
extension of PC, read and written by every instruction. That state does
*not* come from the page tables. If the state is set to Standard Mode (the
state required at ABI boundaries), then all 32/48/64-bit instructions leave
it set in Standard Mode and it is completely backward-compatible with
PowerISA v3.1. Only 16-bit instructions can set it to Compressed Mode (and
not all of them do, there are 16-bit instructions that go Standard Mode ->
Standard Mode).

Jacob