[Libre-soc-dev] daily kan-ban update 18nov2020

[Tobias Platen]

yesterday and today: reading dcache.py and loadstore1.vhdl,  
  deciding which changes may be needed in mmu.py or dcache.py,
  looking for ways to report change of DSISR and DAR to CPU.
  
The Data Storage Interrupt Status Register (DSISR) contains the exception reason,
and the The Data Address Register (DAR) points to the address where the exception
occured. When an exception occurs they are set.

if exception = '1' and r.instr_fault = '0' then
    v.dar := addr;
    if m_in.segerr = '0' and r.align_intr = '0' then
        v.dsisr := dsisr;
    end if;
end if;

-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>