[Libre-soc-dev] avoiding huge combinatorial mux-messes

[Luke Kenneth Casson Leighton]

paul, mikey,

just perusing this:
https://github.com/antonblanchard/microwatt/blob/master/fpu.vhdl#L658

which is another mux-to-select-a-register :)

how we would do this in LibreSOC is: have a completely separate
pipeline (Function Unit) for FP<->INT.  the register profile for that
unit would be:

* 1x FP read
* 1x INT read
* 1x FP write
* 1x INT write

that pipeline/FSM/FunctionUnit could actually handle sqrt (and other
1-reg to 1-reg FP operations) as *well* (by having duplicate copies of
the sqrt FSM *not* by trying to multiplex into the 1 same sqrt FSM:
the idea is to *avoid* MUXing, not add it!).

then the only locations where MUXing takes place is on:

* the broadcast buses for RA connecting all "operand 1" INT pipeline reads
* the broadcast buses for RB connecting all "operand 2" INT pipeline reads
* ... etc.
* ... etc

you then have the opportunity to do away with RS-RA muxing inside a
given pipeline because you'll find that anything that deals with RS
has a *different* register profile from anything that deals with RT.

we dealt with this in LibreSOC by actually deciding that RS doesn't
exist.  in the CSV files (decode1.vhdl) we decided to add "RS" as a
selector for decode_ra().  there are no 3-operand pipelines RS RA RB,
there is only src1 src2.

this again cuts down MUXes.

l.