[Libre-soc-dev] mfocr and mtocrf v3.0B spec ambiguity
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Aug 28 11:50:36 BST 2020
On Fri, Aug 28, 2020 at 9:43 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On Friday, August 28, 2020, Paul Mackerras <paulus at ozlabs.org> wrote:
>> Well, only if compilers or assembly language programmers use mfocrf
>> with more than one bit set in FXM, which would be a perverse thing to
>> do...
>
> :)
>
> they aren't likely to, i would agree, if they don't know it's possible. still, clarifying the spec here to take into account bit 20 is.. sensible.
ah.
i did a first cut implementation in nmigen HDL, then was puzzled as to
why the unit test for the simulation failed. of course, the simulator
uses the v3.0B pseudocode which, of course, i hadn't yet updated.
duh.
# Move To One Condition Register Field
XFX-Form
* mtocrf FXM,RS
Pseudo-code:
count <- 0
do i = 0 to 7
if FXM[i] = 1 then
n <- i
count <- count + 1
if count = 1 then
CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
else CR <- undefined
wait... ah :) i don't mean bit 20, do i - i mean (IBM MSB0 numbering)
bit 11. apologies for the coincidence that in microwatt source code,
insn[20] is POWER9 XFX-Form bit 11. when looking at the XFX-Form i
thought, "oink, bit 20 is reserved". sorry about that.
# 1.6.9 XFX-FORM
|0 |6 |11|12 |20|21 |31 |
| OPCD | RT |1 | FXM |/ | XO | / |
| OPCD | RS |0 | FXM |/ | XO | / |
| OPCD | RS |1 | FXM |/ | XO | / |
i will need to alter the pseudocode so that it no longer has
"undefined" behaviour, simply selecting the highest priority (one-hot)
and always placing a value into CR. there should be no need to have a
new field (modify section 1.6.9).
likewise the mfocrf pseudocode would need altering to ignore "if count
= 1" and always select a one-hot.
am i right in thinking that the for-loop does not need altering? that
it can just be this:
do i = 0 to 7
if FXM[i] = 1 then
n <- i
CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
or does it need to be:
do i = 7 to 0 # inverted order
if FXM[i] = 1 then
n <- i
CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
l.
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