[Libre-soc-dev] daily kan-ban update 27aug2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Aug 27 19:13:30 BST 2020
On Thursday, August 27, 2020, Cole Poirier <colepoirier at gmail.com> wrote:
> On Thu, Aug 27, 2020 at 10:51 AM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> > On Thu, Aug 27, 2020 at 6:35 PM Cole Poirier <colepoirier at gmail.com>
> > >
> > > How are you going about this?
> > * compiling microwatt core_tb ("make core_tb")
> > * copying tests/1.bin to main_ram.bin (as shown in scripts/make_test.sh)
> > * outputting the log to a file
> > * running litex/florent/sim.py --debug > /tmp/ls.txt
> > * running litex/florent/sim.py --debug --cpu=microwatt > /tmp/mw.txt
> > * doing a diff on ls.txt and mw.txt
> > * when discrepancies are found do a ridiculously laborious process of
> > analysing the *microwatt* core_tb log file to find the XER and CR
> > modifications that you *can't* get out via the DMI interface in sim.py
> > because microwatt doesn't _have_ a way through core_debug.vhdl to
> > _read_ XER or CR.
> > sigh.
> Oy! Quite the process, will this be made significantly easier by the
> patch you just sent the microwatt team? or is that just a minor
it was essential even as part of that insanely laborious process.
without the patch there was no log at *all* of what CR or XER were even set
the "correct" way is to add XER and CR reading to core_debug.vhdl which of
course means adding interfaces to cr_regs.vhdl as well.
unfortunately XER is complicated by half of it being in cr_regs and the
other parts in the "fast" parts of the integer regfile.
this is therefore a lot more work than i am happy with.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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