[Libre-soc-dev] daily kan-ban update 25aug2020

[Luke Kenneth Casson Leighton]

tasks:

*
https://bugs.libre-soc.org/showdependencytree.cgi?id=383&maxdepth=1&hide_resolved=1

today:

* set up an irc bot for logging #libre-soc on freenode (hooray!)

* tracked and found a fundamental misunderstanding about CR0 / SO.

creation of CR0 always requires SO as input, even for pipelines that do not
modify it.

therefore, logical and shiftrot, both of which do not alter OV or SO, still
require SO to be an input operand, to be passed through all pipeline
stages, and out the other side.

the addition of this extra field is a fairly extensive modification.
simple enough, but again a surprise that it's taken this long to notice.

change of topic: jacob the DIV FSM is not producing correct output and
needs some high priority attention.  the incorrect output means i cannot
test anything on the FPGA because the DIV pipe is way too large.

l.



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