[Libre-soc-dev] daily kan-ban update 14aug2020

[Luke Kenneth Casson Leighton]

today and yesterday:

in the middle of a complex analysis of litex ecp5 fpga compilation.

the problem encountered is that there are large combinatorial chains which
are impacting the maximum clock rate.

yesterday involved making an absolute dog's dinner mess, mostly of the Comp
Unit Managers.

this afternoon i finally managed to track down that the decoder through to
regfile read are (were) one massive chain.

the POWER9 instruction decoder itself is so comprehensive that it
absolutely cannot be part of any other "stage", and needs its own clock
phase.

pdecode2 was previously part of core, and i have moved it into issuer where
the FSM dedicates a tick to it.

unfortunately in the process of doing that, several other things got messed
up / even fixed.  hrfid was missing for example but a prior bug meant that
it was ignored.

hilarious.

fixing that in turn exposed a bug in the ISA simulator parser...

all this just to get above 55mhz which due to a limitation in the versa
ecp5 LFE5UM FPGA board is the absolute minimum at which the DDR3 IC can run.

with 2x the core clock speed being tied to the DDR3 clock (because doing
otherwise needs clock domain synchronisation) amything below 2x 55mhz the
DDR3 RAM IC simply will not run, at all.

a limitation in litex involving the 32 to 64 bit wishbone bus converter we
are *just* at the threshold (56 mhz) is the limit due to a critical path
chain in litex...

any 32 bit core is perfectly fine and may run at 75 mhz or above because
the converter is not engaged...

urr.....

one thing after another.  just have to be patient.

l.



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