[Libre-soc-dev] ASIC/FPGA discrepancies (was Re: daily kan-ban update 12aug2020)

[whygee at f-cpu.org]

On 2020-08-13 07:51, Lauri Kasanen wrote:
> On Wed, 12 Aug 2020 16:11:20 -0700
> Samuel Falvo II <sam.falvo at gmail.com> wrote:
> 
>> I could be talking out my rear; but, I'm willing to bet that if we had
>> transistor-level control of the circuit, we could basically do
>> whatever we wanted to achieve our speed goals.
> 
> At the cost of taking an eternity :P
> 
> AMD used to lay down some blocks like that (perhaps in big cores they
> still do), but in Bobcat they moved to synthesized logic. Bigger and
> slower, but much quicker to do, and was easily transferred to other
> fabs.

Yes, transistor-level designs have been done and re-done for years now,
and the major design rules are now well understood and integrated in
higher levels. But the rules evolve with each new evolution of the
processes...

I'm taking an intermediate route :
I select "standard gates" and map my designs with/around them.
That's one reason why I created this library
https://hackaday.io/project/162594-vhdl-library-for-gate-level-verification
it helps me target a generic technology and test the design
not only in simulation but also on real silicon (on the ProASIC3 FPGA).
It should be quite technology-independent and then
I check if all the gates are available in
http://www.vlsitechnology.org/html/cells/wsclib013/ for example.

Of course it takes much longer than if I used "classic" synthesis
techniques but I still have a good control over most parameters.

Oh and the FORTH cores were designed on "very mature technologies"
that were far simpler than today's. Many rules have evolved
and will change from one fab to another. Gate-level (instead of
transistor-level) is a decent compromise.

> - Lauri
yg