[Libre-soc-dev] dsily kan-ban update 13aug2020

[Luke Kenneth Casson Leighton]

tasks:

*
https://bugs.libre-soc.org/showdependencytree.cgi?id=383&maxdepth=1&hide_resolved=1

yesterday:

* libre-soc openpower microwatt meeting
* first FPGA boot at 16mhz
* messing with regfiles

today:

* created a binary addressed regfile type with combinatorial read response
*and* writethru.

interestingly this does not fix the latency on pipelines.  next step will
be to attempt a sync delay in MultiCompUnit.

sigh.

l.



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