[Libre-soc-dev] ASIC/FPGA discrepancies (was Re: daily kan-ban update 12aug2020)

[Samuel Falvo II]

On Wed, Aug 12, 2020 at 6:58 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> > You have to remember that your architecture comes from a 60s era system,
> > when people were allowed to think in 3D and make funky stuff like NOR
> > latches.
>
> well, the issue i think is more that it's an out-of-order design.  a

My KCP53000 implementation was limited to about 25MHz as I recall as
well (on Xilinx 3-type part); and it's nowhere near as resource heavy
as Libre-soc.  My inspiration was significantly newer than the CDC; it
was the 6502, which was also limited to 2D geometries.

Yet, there's the F18A core used in the GreenArrays GA144 chip, which
at .18u runs 600 MIPS/core (roughly; each core runs asynchronously
w/out a clock) at room temperature.  Although the stack architecture
is incredibly simple in comparison to the Power ISA processor, I still
don't think that explains its speed at that node.  Not entirely, at
least.

I think what the F18A has in common with the 6502 and the CDC-6600 is
that the engineers had direct input on how individual gates, and even
the very transistors themselves, are used and laid out in the circuit.
Bill Mensch and Chuck Moore laid out each transistor by hand in their
respective cores.  They also use synchronous logic, asynchronous
logic, and pass-gates with impunity in their respective designs.
There are parts of the NMOS 6502 which are edge-clocked and parts
which are level-clocked, for example.  The F18A was simulated in the
analog domain complete with transistor heating models (since it's an
async design, temperature affects gate propagation delays).

I could be talking out my rear; but, I'm willing to bet that if we had
transistor-level control of the circuit, we could basically do
whatever we wanted to achieve our speed goals.

-- 
Samuel A. Falvo II