[Libre-soc-dev] daily kan-ban update 12aug2020

[Luke Kenneth Casson Leighton]

tasks:

*
https://bugs.libre-soc.org/showdependencytree.cgi?id=383&maxdepth=1&hide_resolved=1

yesterday:

* got litex versa ecp5 FPGA build "working" except not initialising DRAM,
the serial console shows the litex BIOS messages.

investigation with help from daveshah showed that the litex initialisation
of the ecp5 ties the DDR3 Clock to the system clock.

because of the massive regfile broadcast buses (20 to one) the routing is
so enormous that it is only possible to achieve 16 mhz.

today:

very annoyingly, investigate replacing the unary int and fast regfiles with
binary-addressed ones.  this may allow FPGA SRAMs to be used.

i really do not like the idea of designing for FPGA targets when we are
doing an ASIC.

the alternative is to see if anyone from litex can set up an alternative
PLL separating the DDR3 clock from the main system clock.

l.



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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68