[Libre-soc-dev] 3D MESA Driver

[Luke Kenneth Casson Leighton]

On Mon, Aug 10, 2020 at 7:16 AM Lauri Kasanen <cand at gmx.com> wrote:
>
> Hi,
>
> In these examples the source was an immediate.

yes.  less to type / think :)

> If the source is a
> register, what controls if the source is looped?

there are two schemes:

* SVPrefix.  this specifies a small subset of permutations as to which of
source and dest registers are vector and which scalar

* VBLOCK aka "Vector Block" which is a much more comprehensive "register
tagging" scheme.  registers are *individually* "tagged" as to whether they
are scalar or vector.

in VBLOCK the *use* of a src or dest reg determines whether they are scalar
or vector and also the tags can apply alternative elwidths.

i will have to look up the notes again because polymorphic widths are a bit
of a pain in hardware.

> e.g.
> "add this one source reg to this range of dst regs"
> "add this range of source regs to this range of dst regs" (which may
> partially overlap for interesting tricks, unless the standard prohibits
> that)


no it does not prohibit that, because it requires extra hardware to do so.

the loop simply ends at the first operation involving a scalar.

this does not sound sensible until you appreciate that predication is
involved.  so the loop actually ends after the first nonzero bit is
encountered in the predicate.

> And it also brings up the reverse operation, a gather, where source is
> looped but destination is not.

all operations are looped: it is just that registers marked as scalar their
index does not increment.

> "add this range of source regs to this one dst reg"

all handled with predication.

in this case the source register index (offset) would increment whilst the
dest register index (offset) would not.

if no predicate was specified then obviously the loop would terminate
immediately.

if however a predicate is specified, then the loop continues skipping over
zero bits, incrementing the *source* register index (offset), 0 skip 0 skip
0 skip until finally a 1 was encountered.

after the one (and only one) element operation occurs, involving the (one)
scalar dest register, the loop is terminated.

this is how gather is done.  as you said, scatter is the other way round,
where the source is scalar, dest is a vector, and predication (first
nonzero bit) determines which element of the dest is "selected".

it gets really fun for "twin predication".  yes it is possible to have a
*completely different* predicate for both src and dest.

only certain operations have this behaviour.  MV, LD, ST, EXTS.  anything
arithmetic involving 2 or more operands do *not* permit twin predication.

twin predication combines both scatter and gather and is entirely novel.

l.




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