[Libre-soc-bugs] [Bug 1157] Implement poly1305

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1157

--- Comment #49 from Sadoon Albader <sadoon at albader.co> ---
(In reply to Luke Kenneth Casson Leighton from comment #48)
> p.s. good progress :)

Thanks :)

I'm actually focusing on the add/mul part since it's the bulk of the work, I
can deal with sv.dsrd later.

I've edited the python code a bit to show the full picture:

            d0=MUL(h0,r0);d=MUL(h1,s2);d0=ADD(d0,d);d=MUL(h2,s1);d0=ADD(d0,d);
            d1=MUL(h0,r1);d=MUL(h1,r0);d1=ADD(d1,d);d=MUL(h2,s2);d1=ADD(d1,d);
            d2=MUL(h0,r2);d=MUL(h1,r1);d2=ADD(d2,d);d=MUL(h2,r0);d2=ADD(d2,d);

The dependencies here only apply to add, meaning we can do 9 multiplications
first in one go, and then add twice (assuming d here is a separate GPR for each
multiplication).

Now, I was about to do this like I assumed in #19, but let's take a second look
at this:

We have h0,h1,h2; r0,r1,r2; s1;s2

The multiplication occurs as follows:

d0 = h0r0 + h1s2 + h2s1
d1 = h0r1 + h1r0 + h2s2
d2 = h0r2 + h1r1 + h2r0

If we arrange the registers like this:
[r2,r1,r0,s2,s1]
 1  2  3  4  5
We can do this:

setvl to 3
sv.mul *RT, *h, *3
sv.mul *RT, *h, *2
sv.mul *RT, *h, *1

Perfectly reasonable, but I don't like this. These muls can be one sv.mul if we
arrange things correctly. I think we need svindex but am still trying to learn
svindex and svremap.

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