[Libre-soc-bugs] [Bug 980] Implement C-based Power ISA pseudocode compiler

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=980

--- Comment #100 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #95)

> ...where assignments to registers (and similar stuff) have the flags
> updated. What's the point of having ok

i explained already, jacob can you explain it, it matches the hardware.
but briefly so that time is not wasted.

> Even omitting issues related to global context in general, this is a detail
> of a particular implementation, the low-level architecture should be kept
> out of these details. I don't want the implementation to be tied to a
> particular language;

that's unrealistic (i haven't time to explain, so sorry)
and very much out of scope

> at some point we might opt to reuse this generated code
> not only from C++. 

well beyond scope and not appropriate for discussion right now
due to time pressure.

> We might have wrappers which fetch/store parts of the
> state though in order to keep the context opaque.

indeed. that's exactly how i managed to turn a scalar RISC-V simulator,
spike, into a FULL Simple-V Vectorised simulator, in only 6-8 weeks.
but the wrappers were done by #including a template around each
scalar instruction, and all of the (equivalent of) oppc_* were
class/template members of that class.

no ctx pointer.

no XLEN member variable in ctx.

all done by c++ overloads.

please, really, don't add extra programming languages to this code,
even as a planned future consideration.

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