[Libre-soc-bugs] [Bug 1248] New: sv.creqv (and others) do not encode/decode vector reg numbers correctly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1248

            Bug ID: 1248
           Summary: sv.creqv (and others) do not encode/decode vector reg
                    numbers correctly
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

the numbering (EXTRA3) and encoding for sv.cr* operations
(5-bit) is hosed. this is not a surprise as it has never
been tested. unit test time....

-- 
You are receiving this mail because:
You are on the CC list for the bug.