[Libre-soc-bugs] [Bug 1246] New: Rc=1 vector output of CRs is going solely into CR0

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1246

            Bug ID: 1246
           Summary: Rc=1 vector output of CRs is going solely into CR0
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

this needs fixing in power_decoder2.py

            for i, stuff in enumerate((
                ("RA", e.read_reg1, dec_a.reg_out, in1_svdec, in1_step, False),
                ("RB", e.read_reg2, dec_b.reg_out, in2_svdec, in2_step, False),
                ("RC", e.read_reg3, dec_c.reg_out, in3_svdec, in3_step, False),
                ("RT", e.write_reg, dec_o.reg_out, o_svdec, o_step, True),
                ("EA", e.write_ea, dec_o2.reg_out, o2_svdec, o2_step, True))):

RT and EA. also needed vector of CRs

                    with m.If(cr.sv_override == 1):  # CR0
                        offs = SVP64CROffs.CR0
                        comb += to_reg.data.eq(step+offs)

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