[Libre-soc-bugs] [Bug 980] Implement C-based Power ISA pseudocode compiler

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=980

--- Comment #48 from Dmitry Selyutin <ghostmansd at gmail.com> ---
I had to cheat a bit to force output of RA instead of (RA) for constructs like
assignments and subscripts (the default is (RA), but subscripts and assignments
are different).

I dropped everything related to "read_regs", "uninit_regs" and other stateful
bits from the copy of the parser. That's job of the concrete visitor, not the
parser.

The pseudocode visitor hooks look like this:

    @Hook(pc_ast.IfExpr)
    def IfExpr(self, node):
        yield node
        stmt = " ".join([
            "if",
            str(self[node.test]),
            "then",
        ])
        self[node].emit(stmt=stmt)
        for (level, stmt) in self[node.body]:
            self[node].emit(stmt=stmt, level=level)
        if node.orelse:
            self[node].emit("else")
            for (level, stmt) in self[node.orelse]:
                self[node].emit(stmt=stmt, level=level)

    @Hook(pc_ast.WhileExpr)
    def WhileExpr(self, node):
        yield node
        stmt = " ".join([
            "do",
            "while",
            str(self[node.test]),
        ])
        self[node].emit(stmt=stmt)
        for (level, stmt) in self[node.body]:
            self[node].emit(stmt=stmt, level=level)
        if node.orelse:
            self[node].emit("else")
            for (level, stmt) in self[node.orelse]:
                self[node].emit(stmt=stmt, level=level)

Obviously there's a lot of other hooks, not shown here for brevity.

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