[Libre-soc-bugs] [Bug 1212] NLnet 2023 Simple-V RISC-V binutils

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1212

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok we got the "1st stage acknowledgement passing to 2nd" message, hooray.
next phase involves as usual having the full list of milestones with
budgets, remember we had these, they each need a bugreport and
budget, in comment #0 in the usual format like every other grant
(eventually).

* Completion of libopid (an instruction database parser)
* Completion of libopid porting of Libre-SOC infrastructure both Scalar Power
ISA
  and SVP64/Power (currently based on an early iteration of libopid)
* Definition of assembler and disassembler for RISC-V
  instructions and also SVP32, 48 and 64 Vector Prefixing formats, using
libopid
* Completion of definitions of Simple-V/Single formats SVP64Single, SVP48Single
and SVP32Single
  and implementation support of the same for both Power and RISC-V
  (https://libre-soc.org/openpower/sv/svp64-single/)
* Test vectors for libopid and binutils
* Documentation, demonstrations and Conference Papers.

-- 
You are receiving this mail because:
You are on the CC list for the bug.