[Libre-soc-bugs] [Bug 982] Support PowerPC ABI in ISACaller

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Oct 22 21:46:07 BST 2023


--- Comment #128 from Dmitry Selyutin <ghostmansd at gmail.com> ---
(In reply to Dmitry Selyutin from comment #123)
> SRR1 gets its bit 17 set, but I'm struggling to find this bit anywhere.

Seems it's caused by this line:

self.spr['SRR1'][trap_bit] = 1  # change *copy* of MSR in SRR1
trap_bit is PIb.TRAP, which is 46, which is (64 - 17 - 1).

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