[Libre-soc-bugs] [Bug 982] Support PowerPC ABI in ISACaller

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Oct 22 14:38:30 BST 2023


--- Comment #118 from Dmitry Selyutin <ghostmansd at gmail.com> ---
If I understand correctly, we must introduce some code residing at 0xc00, but I
cannot think of a good way to handle it yet. We must either modify the Program
so that every program has an additional code but this totally breaks the
principle of least astonishment.

FTR, here's what I get for MSR mismatch:
  File "./src/openpower/decoder/isa/test_syscall.py", line 23, in
    self.assertEqual(sim.msr, 0xffffffffffffffff)         # MSR changed to this
by sc/trap
SelectableInt(value=0xfbfffffefd7f10c5, bits=64) != 18446744073709551615

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