[Libre-soc-bugs] [Bug 1044] SVP64 implementation of pow(x,y,z)

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Oct 10 08:45:26 BST 2023


--- Comment #47 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #46)
> the assumption that you are making is one that a *SIMD* architecture
> has because the ISA directly connects to the back-end hardware.

no, i was thinking of vertical-first mode, not SIMD. I do know how it works,
having read your explanations for years and having read about how Mitch Alsup's
cpu design works.

> it basically is not your problem "as an assembler writer" to
> worry about what hardware does, because there is no direct connection
> (unlike in a SIMD ISA).

it *is* my problem, because:
* the code I write directly determines code size, which is what we're
optimizing for here.
* the data-flow graph of the code I write directly determines minimum latency
even if the cpu has effectively infinite resources. you can't escape Amdahl's
law. not even if you have a monster cpu with all the fanciest SV features.

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