[Libre-soc-bugs] [Bug 1079] make LD/ST-with-update EXTRA3

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1079

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
this is awkward:

class BaseRM(_Mapping):
    _: _Field = range(24)
    mmode: _Field = (0,)
    mask: _Field = range(1, 4)
    elwidth: _Field = range(4, 6)
    ewsrc: _Field = range(6, 8)
    subvl: _Field = range(8, 10)
    mode: Mode.remap(range(19, 24))
--> alternative_smask: _Field = (6,7,19) <- special-case: LDST_IDX
    smask: _Field = range(16, 19)        <- everything else (not LDST_IDX)
    extra: Extra.remap(range(10, 19))
    extra2: Extra2.remap(range(10, 19))
    extra3: Extra3.remap(range(10, 19))

now, by a happy coincidence - i think - it is possible to hit this:

   * EXTRA2 : 0: [10,11] 1: [12,13] 2: [14,15] 3: [16,17] unused: [18]
   * EXTRA3 : 0: [10,11,12] 1: [13,14,15] mask: [16,17,18] 
   * EXTRA32: 0: [10,11,12] 1: [13,14,15] 2: [16,17] mask: [6,7,18]

with this:

*    RT - BaseRM.extra3[0] - bits 10,11,12
*    RA - BaseRM.extra3[1] - bits 13,14,15
*    RB - BaseRM.extra2[3] - bits 16,17

hooray!  yes.

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