[Libre-soc-bugs] [Bug 1086] ls2 verilator sim - setting up chroot and documentation

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon May 22 14:18:46 BST 2023


--- Comment #10 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
(In reply to Andrey Miroshnikov from comment #9)
> Will update on the results tomorrow.

Re-ran the devscripts.
Looking back at IRC log from January 17th, saw Luke's thought on running
hdl-tools-yosys before hdl-dev-repos, and so I did:

After running hdl-tools-yosys, no nmigen was installed (good, expected

After running hdl-dev-repos, I was able to build the soc successfully. All the
nmigen libs were still at 0.1 (which both Jacob and Luke mentioned in the above
IRC log is an older version than the 0.3 or 0.2). Is this a problem?

c4m-jtag               0.1.dev152+gf5322d8 
nmigen                 0.1.dev1205+g29dec30         
nmigen-boards          0.1.dev217+ga949308  
nmigen-soc             0.1.dev53+gfd2aaa3     
nmigen-stdio           0.1.dev7+g475cb6f
pyvcd                  0.2.4

The hdl-dev-ls2 added the other modules without changing nmigen or pyvcd (good,
expected behaviour):
gram                   0.1.dev546+g35dab52
lambdasoc              0.1.dev86+gd15878b

I tried running 'make clean' of the soc repo (before re-generating external
core), I get an error related to a depricated Jinja function.
ImportError: cannot import name 'contextfunction' from 'jinja2'
make: *** [Makefile:127: clean] Error 1

The version pip installs is this:
Jinja2                 3.1.2

After a quick search, this github issue shows that 'contextfunction' has been
depricated since Jinja 3.0, but could be bodged by using the newer function
(see https://github.com/tgen/jetstream/issues/139)

Turns out the Makefile doesn't have a 'clean' rule, and it's actually running 
" Catch-all target: route all unknown targets to Sphinx using the new
"make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS)."
I guess this is for document generation?

Generating the FPGA bitstream with hello_world worked and I was able to run it
on fpga. The flow up to this point has been validated (will add
fpga-boot-load-prog-install script to the wiki page).
I'll continue with the verilator sim.

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